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Phase Locked Loop Based Tunable Clock Generator for ADC & DAC

This project involves the design of a phase-locked loop (PLL) based tunable clock generator, incorporating a Phase Detector (PD), Loop Filter (LP), Oscillator, and Clock Dividers. These components work together to provide stable and accurate phase synchronization. The design features a 2nd order loop filter and a Voltage-Controlled Oscillator (VCO) with differential output frequencies ranging from 180-200 MHz and 90- 110 MHz, catering to the ADC and DAC needs of lab bench setups for Analog Discoveries. It achieves impressive performance metrics, including a jitter of 500 fs and phase noise of less than -100 dBc/Hz at 1 MHz. The design has been implemented and simulated using open-source IC design tools: Xschem, Netgen, Magic, and KLayout, using the GF180mcu process design kit (PDK).

Featured Projects

12-Bit Segmented Current Steering DAC

A 12-Bit Segmented Current Steering digital-to-analog converter (DAC) was designed on GF18MCU PDK. The DAC achieves an update rate of 10 MS/s and an effective number of bits (ENOB) greater than 9, with intermodulation distortion better than -60 dB. The most significant bits (MSBs) are implemented using thermometer coding (unary), while the least significant bits (LSBs) utilize binary coding. The design achieves a maximum differential nonlinearity (DNL) of 0.39 LSBs and an integral nonlinearity (INL) of -0.83 LSBs.

  • Update rate of 10 MS/s, ENOB greater than 9.
  • Thermometer coding for MSBs and binary coding for LSBs.
  • DNL: 0.39 LSBs, INL: -0.83 LSBs.
12-Bit Segmented Current Steering DAC Layout

Layout of 12-Bit Segmented Current Steering DAC

12-Bit Segmented Current Steering DAC Block Diagram

Block Diagram of 12-Bit Segmented Current Steering DAC

Differential Clock Generator

The primary goal of the proposed Phase-Locked Loop (PLL) is to generate a differential, 1 MHz to 128 MHz programmable clock with step size of 1 MHz. This design is meticulously crafted to minimize jitter and phase noise, ensuring a high Signal-to-Noise Ratio (SNR) in data converters. The Phase-Locked Loop (PLL) consists of Phase Frequency Detector (PFD), Charge Pump, Loop Filter, Voltage Controlled Oscillator (VCO), and Programmable N-Divider.

  • 1 MHz to 128 MHz programmable clock.
  • Minimized jitter and phase noise for high SNR.
  • Includes PFD, Charge Pump, Loop Filter, VCO, and Programmable N-Divider.
Differential Clock Generator Layout

Layout of Differential Clock Generator

Differential Clock Generator Block Diagram

Block Diagram of Differential Clock Generator

AWG Mux and Signal Conditioning

The AWG Mux and Signal Conditioning module, part of a "lab bench on a chip" system, features several components: transimpedance stage, buffer, differential op-amp, low-pass filter, and differential DEMUX. The design meets the required specifications of 5.3 MHz bandwidth, 138 mV/µs slew rate, and 497 fF load capacitance. Utilizing a cascode folded op-amp, it achieves high bandwidth, slew rate, and gain. This configuration ensures precise signal conditioning and waveform generation, making it effective for analog circuit characterization and testing.

  • 5.3 MHz bandwidth, 138 mV/µs slew rate, 497 fF load capacitance.
  • Transimpedance stage, buffer, differential op-amp, low-pass filter, and DEMUX.
  • Effective for analog circuit characterization and testing.
AWG Mux and Signal Conditioning Layout

Layout of AWG Mux and Signal Conditioning

AWG Mux and Signal Conditioning Block Diagram

Block Diagram of AWG Mux and Signal Conditioning