Conformal Low Power GXL | Virtuoso AMS Designer Environment | Innovus Mixed Signal Option |
Genus Low Power Option | Virtuoso Schematic Editor | Innovus Hierarchical Design Option |
Genus Physical Option | Virtuoso ADE Assembler | Innovus Implementation System |
Genus Synthesis Solution | Virtuoso Layout Suite GXL | JasperGold Formal Verification Platform |
Cadence SKILL Development Environment | Voltus-Fi Custom Power Integrity Solution XL | Modus DFT Option |
Virtuoso- Schematic Editor Verilog Interface | Allegro Venture PCB Designer | Modus ATPG Distributed Base |
Cadence Pegasus 16nm Node | Cadence Quantus Extraction XL | Tempus Timing Signoff Solution XL |
Cadence Pegasus Design Rule Check | Sigrity Advanced SI II | Voltus IC Power Integrity Solution XL |
Cadence Pegasus Layout vs. Schematic Check | Spectre RelXpert Reliability Simulator | Tempus Timing Signoff Solution ECO |
Cadence Pegasus DFM Fill | Spectre AMS Designer | Manager Project Server |
Keysight Advanced Design System (ADS) |
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TSMC Process Development Kits (Pdks) integrated witrh licencesd Cadence Tools |
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180nm CMOS | 130nm CMOS | 65nmCMOS |
28nm CMOS | 180nm BCD | |
Have access for techologies available through CMP & AMS |
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Have well establishedecosystem of open source Analog, Digital & Mixed Signal ICD Tool Suite |
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